Optical waveguide devices are typically made on silicon substrates. It is desirable that materials used for optical waveguides exhibit certain optical, thermal and mechanical characteristics, besides low optical loss. Common silicon micromachining technologies include anisotropic wet etching and dry reactive ion etching (RIE). Passive optical waveguides exhibiting acceptable losses between 0.1 and 10 dB/cm have been demonstrated in a number of materials, most notably optical grade glasses (silica) and PMMA and polystyrene polymers. The highest quality silica waveguides with very low losses of 0.1 dB/cm have been deposited on silicon wafers by flame hydrolysis, which yields good control over the index and thickness of the film but requires heating the porous glass layer to 1250° C. for consolidation. This high temperature perturbs the crystallographic microstructure of silicon, which affects its anisotropic wet etching. Furthermore, the flame hydrolysis technique requires specialized and expensive equipment and involves the use of silane, which is a toxic gas.
The fabrication of ridge waveguides in silica and polymer requires etching to a depth of several microns. Deep vertical sidewalls with high aspect ratios can be obtained in silicon with RIE. However, RIE is an expensive process, which requires the use of high vacuum equipment. Deep RIE requires the use of high selectivity gases and appropriate masking layers. Silicon dioxide can be used effectively to mask silicon because it has a very high selectivity ratio of 200:1 for certain etching gases. This allows etching of several hundred microns deep silicon structure with an oxide layer of only a few microns. Deep etching of polyimide is problematic because there is no known masking material with high selectivity ratio toward polyimide. A polyimide substrate cannot withstand the high temperatures necessary to deposit an oxide film. Photoresist, being a polymer, does not have high selectivity toward polyimide. Metallic films, such as titanium or aluminum, are used effectively to mask polyimide. However, etching of polyimide has been limited to a depth of a few microns due to erosion of the metal masking layer. The highly energetic plasma ions cause the metallic layer to sputter and deposit metal particles on the polyimide terminating the etching. The lack of suitable masking material for polyimide has been a limiting factor in the use of RIE.
It is desired in certain applications to incline the end faces of cantilevered film waveguides relative to the axis of the waveguide, especially at air gaps between cantilevered and fixed waveguides. This cannot be readily achieved with RIE because the electric field lines in a plasma, which define the trajectory of the energetic ions terminate perpendicularly to the wafer surface. Thus, the desired oblique walls at the end faces cannot be obtained with silicon micromachining technology.
Silicon micromachined cantilevers carrying film waveguides have made use of films such as silicon dioxide (silica) and nitride. There are problems associated with fabricating microstructures from the bulk of silicon substrates, for example the undercutting of convex corners, which alters the shape of microstructures, e.g. the inertial mass at the end of a cantilever. This prevents the reproducible fabrication of microstructures with 90° corners. This problem can be partially corrected with the use of proper corner compensation in the mask layout, however this requires significant experimentation by trial and error to determine the correct compensation for each mask design. Another problem with using silica films for waveguides in micro-mechanical applications, which is not encountered in micro-electronic processing, is that thick films (up to 50 μm) are needed. The problem with thick films is that they tend to crack and peel off due to the large residual stresses built-in during deposition due to the mismatch between the coefficients of thermal expansion of the film and substrate. Furthermore, the deposition of silica films is not compatible with silicon micromachining because it requires heating the wafer to a very high temperature, which may alter the crystallinity of silicon on which anisotropic etching depends. Another drawback of high silica films is the necessity of deep RIE to form ridge waveguides, which is an expensive process and which is limited due to mask erosion.
Certain polymers have been used as waveguide materials. Low loss polymer waveguides have been most commonly achieved in poly-methyl-methacrylate (PMMA) or polystyrene. However, polymers are affected by bases such as KOH or NaOH, which are used in anisotropic silicon micromachining. The use of polyimides on silicon presents problems in regards to wet and dry etching and to the mismatch in the coefficient of thermal expansion, so that polyimide films on silicon wafers tend to have limited utility in fabricating micromachined structures for optical wave guiding applications.
Polymer film waveguides that are spun cast on planar substrates exhibit thermal and optical properties that are dependent on the deposition parameters. In particular, the degree of anisotropy, such as the difference between the indices of refraction (birefringence), and the difference between the coefficients of thermal expansion (CTEs) along directions that are perpendicular and parallel to the surface of the substrate, depend on the level of stress that is induced in the film during fabrication due to the mismatch between the planar CTEs of the film and substrate. For mechanical ruggedness and in order to avoid peeling off or delamination of the film, it is desired to reduce the CTE mismatch as this reduces the level of stress at the interface between the film and substrate. For optical and especially wave guiding applications, it is desired to reduce the birefringence of the film. The planar CTE of a highly anisotropic polymeric film can be as low as 6 ppm/° C., while the perpendicular CTE can be as high as 150 ppm/° C. An isotropic polymeric film has both parallel and perpendicular CTEs about 50 ppm/° C. Most polymers have CTEs that are considerably larger than that of silicon, which is about 3 ppm/° C. When polymeric films are deposited on silicon wafers for electronic applications, the planar CTE of the film is chosen as small as possible to minimize the mismatch with silicon. While this reduces the stresses, it creates a highly anisotropic film, which is undesirable for optical wave guiding applications. Thus, it has not been possible to simultaneously reduce the stresses and minimize anisotropy and birefringence in a polymeric film on a silicon wafer.
The residual side wall angle of a wet etched film is unpredictable due to the swelling when a developed film dries at elevated temperatures. This is aggravated in multilayered films because the solvents of subsequent layers attack the edges of the previous layer at the interface between the layers resulting in uneven side walls.
The properties of most materials change with temperature. The index of refraction is tuned thermally through the thermo-optic coefficient, which is the rate of change of index with temperature. The optical length of a light path is the product of its physical length times the index. A change in temperature causes a variation in length due to thermal strain and a change in index due to the thermo-optic effect. Thermal tuning is used in interferometric devices to change the phase and intensity of light passing through a waveguide. It is desired to achieve temperature-insensitive or athermal design in order to minimize the dependence of the output of optical devices on environmental disturbances, such as fluctuations in temperature. It is important to stabilize the center wavelengths of multi-channel devices such as optical filters, which tend to drift. Further, athermal design lessens the dependence on the polarization of light, which is desirable. This has necessitated the use of temperature control units, which utilize a heater or a Peltier cooler to maintain the temperature of the device constant. Temperature control requires constant electrical power consumption of a few watts and dedicated electronic circuits, which is costly and undesirable. Uncontrolled athermal operation is achieved by balancing the effects of the variations of index and length so that the net change in optical path length is zero. This can be achieved by equating the thermo-optic coefficient to the negative of the product of the index of the film times the CTE of the substrate, assuming that the film is sufficiently thinner than the substrate. This requires films with negative thermo-optic coefficients. Some polymer waveguide materials, such as fluorinated acrylates, have a negative thermo-optic coefficient, which is approximately equal to the product of the index of the film and the CTE of polymer substrates. Thus, athermal design can be achieved with the use of certain polymer films and substrates. However, it is not possible to tune such an optical device thermally due to its temperature-insensitive design.
Quartz and ceramic substrates, such as alumina (Al2O3) are used for RF applications. Metal conductor lines are deposited on the substrates for microwave transmission. The substrate is polished to reduce the loss at the substrate/metal interface. Both materials have extremely low dissipation factors, also known as loss tangent. Quartz has a dielectric constant of about 3.8, while alumina is about 9.9. There is constant drive in the industry to use higher frequencies beyond 30 GHz into the millimeter wave range. As the frequency increases a larger portion of the wave travels in the substrate, a phenomenon known as skin effect. A substrate with a certain thickness can support multiple modes at higher frequency. It is desirable to transmit only the fundamental mode. It is preferable to limit the thickness of the substrate to a maximum corresponding to the cut-off of higher order modes. The maximum thickness for single mode transmission depends on the dielectric constant of the substrate. An alumina substrate, for example, should not be thicker than 250 μm for frequencies above 10 GHz. The use of a very thin substrate is undesirable because it is fragile. A substrate with a lower dielectric constant, such as quartz, can be thicker, for example 500 μm while supporting a single mode at the same frequencies. It is preferable to use thicker substrates with low dielectric constant in the range of 3 to 4 for higher frequencies because it is cheaper to fabricate and easier to handle. However, the use of quartz for RF substrates has been problematic because it is expensive and brittle.
When a silicon wafer carrying a polymer film is cut or cleaved, the polymer film tends to lift off and hang over the cut edge of the wafer. The width of the lifted-off regions can extend up to 300 μm inward from the edge. This necessitates removing the entire lifted region of the film, for example by ablating with a laser to improve coupling of light in and out of the waveguide. However, this is problematic because it creates a relatively long step that the light must traverse between the edge of the wafer and the edge of the film. If this step is at the input edge of the waveguide where light is focused as a cone or wedge then a substantial portion of the light can be blocked off. If the step is at the output edge then it interferes with the collection of the light by a lens for feeding into a pick up fiber. This step is particularly problematic over silicon wafers. It was necessary to control the end face of a polymer channel waveguide within 5 μm from the cleaved silicon substrate edge in order to achieve acceptable coupling of the light (J. C. Chon and P. B. Comita, “Laser ablation of nonlinear-optical polymers to define low-loss optical channel waveguides” Opt. Lett. 19, 1840, 1994). The cleavage of the silicon wafer must be done very carefully so that the least amount of film is peeled off at the cleaved edges.
To couple light in and out of single mode channel waveguides single mode optical fibers are typically attached to the end of the waveguides. This requires alignment of the axes of the fiber and waveguide with submicron accuracy. For example, V-grooves can be etched in silicon substrates and the alignment between the fiber and waveguide is adjusted while actively monitoring the coupling efficiency. At the point of maximum efficiency, the fiber is attached to the substrate. It would be desirable to couple light efficiently between single mode fiber and waveguide passively without monitoring the light intensity during the attachment.
Micro-electro-mechanical (MEMS) devices are fabricated on silicon wafers either by surface micromachining of thin layers deposited on the silicon substrate, or by bulk micromachining of the MEMS structure in the silicon wafer. Bulk-micromachined structures are larger, sturdier and have higher resonant frequencies. Surface-micromachined structures are smaller, flimsier and have lower resonant frequencies. However, bulk-micromachined structures require more driving force and power to move or bend using thin actuating films.
Piezoelectric films, such as PZT or ZnO or AlN, are useful to actuate surface or bulk micromachined MEMS structures, such as cantilevers. It is also desirable to etch deep microstructures with high aspect ratios for the fabrication of micromechanical devices, such as accelerometers and optical switches. The piezoelectric films are layered between metallic films, such as Pt or Al, which form the electrodes. The piezoelectric films are patterned along with the metallic films. RIE has been used to pattern ZnO; and Argon ion beam milling has been used to pattern PZT, both of which are expensive dry etching techniques. A problem with dry etching has been poor selectivity, i.e. the etch rate of the masking layer or other layers in the structure can be comparable to or even exceed the etch rate of the layer that is intended to be etched. This causes low yield and poor dimensional control of ZnO devices, and poor selectivity toward PZT relative to the metallic layers. It also limits the etch depth of MEMS devices to the thickness of the mask layer, and necessitates the use of extra masking layers, which is undesirable.
Polyimide substrates can be used to package microelectronic components, such as chips. Other materials are currently used to accomplish this task including organic and ceramic substrates. As chip functionality becomes more sophisticated and pin count increases, it becomes necessary to provide higher density interconnects among the chips. It is often necessary to route the signals through multi-level substrates in order to avoid wire crossings. This is accomplished by drilling vertical vias in each of the layers of the substrate, which are covered by contact pads on each side of the wafer. Higher density is achieved by reducing the cross-section of the metallic traces in each layer and by reducing the diameter and spacing between holes. Microvias are commonly drilled with lasers, such as excimer or tripled YAG. Very narrow holes with diameters down to 25 μms can be achieved routinely. However, it has been difficult to coat the cylindrical wall of a hole with an aspect ratio greater than 1:1 reliably.
Organic substrate fabrication has traditionally consisted of a lamination of several sheets of organic materials, such as FR-4 epoxy. FR-4 layers are typically between 1 and 3 mils (25-75 μms) thick. The laminate is traditionally drilled using conventional mechanical drilling. One drawback of this technique is that the holes end up at the same locations in all the layers, which wastes board space and prevents the achievement of high density. Further, the different layers of the assembly must have individual hole patterns because the signal routing requirements change from layer to layer. This can be accomplished by drilling the FR-4 layers separately with laser prior to lamination. However, this technique also yields low density because it is difficult to maintain a high degree of alignment between the holes during the lamination process.
Another substrate fabrication technique, which is used widely with ceramic substrates, is the build up process. Starting with a rigid ceramic wafer, successive dielectric and metallic layers are added using thick film technology. Each layer is patterned to create either horizontal metal traces or drilled vertical vias. A thick ceramic paste with metal fillers, such as Fodel manufactured by DuPont, is driven into the tiny holes using a process similar to screen-printing. The substrate is subsequently co-fired at very high temperature to sinter the material. The drawback of the build up process is that the successive layers take the shape of the layers underneath with the resulting loss of planarity and registration accuracy, hence density.
In order to increase the density of the interconnect it is necessary to fabricate smaller diameter holes and to pack them closer together. However, the challenge is not drilling smaller holes. Holes smaller than 50 μm are drilled routinely with laser. The challenge has been coating them with metal to ensure reliable electrical connection between both sides of the substrate. Getting the walls of the tiny holes to wet for the metal to stick to it has proved to be challenging. There are two main parameters, which play a vital role in determining the success of the metallization, namely the diameter of the hole and its aspect ratio, i.e. the ratio of the depth of the hole to its diameter. The current limitation in hole diameter is about 100 μms and the highest aspect ratio that can be successfully coated is about 1:1 or even less.
A seed layer is a precursor for growing a metallic layer on any surface. However, the chemical processes responsible for seeding thin metallic films on flat surfaces are totally different from those that are used to coat vertical cylindrical walls of tiny holes. For example, dry coating techniques such as sputtering and thermal evaporation yield excellent film coverage on flat surfaces but cannot coat narrow holes, particularly those with high aspect ratios. A wet technique, which is widely used in the semi-conductor packaging industry for metallizing 100 μm vias in rigid FR-4 boards, is electroless copper plating. However, electroless plating cannot be used to coat 50 μm or smaller vias because it releases hydrogen bubbles of about the same diameter, which get trapped in the holes and block the plating process. In the case of ceramic substrates the thick Fodel paste cannot penetrate a 50-μm hole. For these reasons, the smallest hole diameter that can be successfully coated in either material is currently limited to about 100 μms; and the pitch, i.e. center-to-center between holes or pads is limited to about 200 μms. Furthermore, it is desired to eliminate the adhesive layer between successive layers of a multi-layered substrate. The use of adhesive layers, such as Pyralux manufactured by DuPont, increase the complexity of the assembly and can become the bottleneck limiting the speed and density of the interconnect.
It is estimated that in the near future about 50% of all silicon wafers and chips will be thinned to make way for 3-D electronics and for better heat dissipation. High performance silicon devices will be stacked to provide high-density circuits. Each silicon layer must be thinned to below 100 microns to meet certain total thickness requirements for mobile and handheld devices. It is also desired to fabricate high performance single crystal silicon devices on flexible substrates for high-density displays and smart cards. The silicon wafers are thinned and diced after fabrication of the devices.
The handling and packaging of thinned silicon wafers and chips presents a major problem due to breakage of the thin wafers, which reduce the yield dramatically. The back-end-of-the-line (BEOL) industry does not have a viable solution for this problem.
It is desired to thin silicon for various applications. Silicon membranes, only a few microns thick, are very flexible and commercially available, albeit very expensive. High performance electronic devices are fabricated using high temperature CMOS processes on standard thickness silicon wafers. The silicon wafers are thinned and diced after fabrication of the devices. Silicon wafers have been thinned down to 20 microns. Many applications require through-wafer via drilling, plating and metallization of the backside of the thinned wafers or chips for interconnection to other devices. This also requires the deposition of solder bumps, which can be even thicker than the wafer. The packaging industry faces a serious problem in handling of thin wafers during processing due to brittleness and fragility of thin silicon. Even if the thin silicon device survives the processing, the final packaging presents additional risks of breakage and further reduction of yield. Thin silicon wafers are not inexpensive. For example, a 100 mm diameter membrane 10 μm thick costs as much as $ 300. 200 mm diameter wafers have been thinned down to 50 μms at very high cost. Even though these wafers are flexible, but they are delicate, fragile and break easily if not handled properly. Processing of wafers after thinning should be avoided as much as possible. Thin silicon wafers and dies require special handling and extreme care, which add cost. It is also desirable to use existing automated robotic handling equipment to handle the majority of wafers.
The most common technique for thinning is back grinding. The silicon wafer is mounted on a supporting carrier, which must withstand the grinding and further processing. The carrier must attach to the wafer firmly and then detach easily after thinning for packaging. Currently most of the effort in the industry is focused on (temporary) handling rather than (permanent) packaging.
The industry is searching for a solution for handling thin wafers throughout the production cycle. All existing solutions are extremely difficult to implement and introduce very high risk of wafer breakage. Equipment and materials suppliers are considering various approaches. Most handling techniques currently being investigated cannot survive all the processing steps.
Several companies are using polymeric tapes made of soft material with Kapton backing. The tape is inexpensive and can effectively support the wafer during grinding but cannot withstand high temperatures encountered during other processing, such as backside metallization. Variations in the thickness of the tape translate directly into thickness variations (TTV) of the thinned wafer. The risk of breakage increases drastically during demounting especially for wafers below 80 μms. Further, the tape is incompatible with standard automated tools because it does not provide a rigid support.
Silicon and glass wafers have been used as temporary carriers of thinned silicon wafers using reversible bonding, i.e. held by wax. The silicon and glass wafers provide rigid support compatible with automated handling but the risk of breakage during de-waxing is still very high. Alternatively, the wafer can be held electrostatically on a chuck, but this solution is expensive and not useful for ultra-thin grinding due to insufficient shear strength. Further, it is incompatible with subsequent processing steps such as etching or elevated temperatures due to dissipation of the charges.
The most critical step for the success of thinning is the choice of glue between the wafer being thinned and the carrier substrate, which depends on whether the bond is temporary or permanent. For temporary handling applications, the glue must be strong enough to provide sufficient shear strength during grinding but also must dissolve easily without leaving any residue. The risk of breakage during de-bonding and cleaning is very high. Most glues can be dissolved either with acetone or by heating. Acetone dissolution is limited by peripheral access, thus requiring die level bonding or the use of a perforated carrier. Sliding the thin wafer at temperatures above the flow point of the glue and subsequent acetone cleaning poses extra risks of breakage. The glue must survive all processing steps including vacuum and high temperature backside metallization and then dissolve without leaving a trace. These are tough requirements. Organic adhesives (epoxies) leave residues. For this reason, the temporary attachment issues are not trivial. The industry does not have a viable solution.
Finding the right method of support during thinning has been a major challenge for the industry. For this reason the majority of the effort is currently directed toward solving the temporary handling problem rather than the long-term packaging issues. The high risk of breakage is due to the need to de-bond the thin wafer after grinding. There is currently no suitable substrate, which supports the silicon wafer during thinning and acts as a permanent carrier.
Thin-film transistors and memory cells have been deposited directly onto flexible substrates. These flexible circuits consist mainly of low density interconnects and low performance devices. This technique is alternative to thinning of chips and mounting on flexible substrates. The main drive is the fabrication of large area electronics, which can be printed while rolled from reel to reel, and for flexible solar panels. The emphasis is on low cost. The films are deposited at relatively low temperatures compatible with the flexible materials. This yields amorphous or poly-crystalline silicon devices.
The drawbacks of polysilicon circuits are that they are too slow due to the gate material being non silicon-oxide. This causes poor performance due to decreased carrier mobility. These devices are fabricated at temperatures, which do not exceed 200° C.-300° C. Growing good gate oxide for high performance MOSFETs, for example, requires temperatures of at least 800° C. Polymeric flexible materials cannot withstand such temperatures. Further, fabs and foundries are reluctant to introduce polymer-based substrates in their MOS lines due to contamination issues. Large area circuits are fabricated using inkjet-printing technology, which yield coarse resolution. For these reasons large area flexible circuits fabricated on sheet or roll are bound to low performance devices.
There is a desire in the industry to fabricate single crystal silicon devices and circuits on flexible substrates. Polymeric films, such as PDMS, have been spun on silicon-on-insulator (SOI) wafers and bare silicon strips, 300 nm thick, were transferred to the PDMS substrate by etching the buried oxide layer with HF. Low performance transistors were fabricated in the single-crystal silicon strips after the transfer. This research was published in the journal “Science” in January 2006.
Silicon dies about 5 mm×5 mm have been thinned down to 20 μms, metallized with about 6-8 μms of copper and flip chip mounted on spun-on polyimide films also 20 μms thick, with significant stress and yield issues. However, high performance single crystal silicon devices and circuit layers have not been transferred to flexible substrates.
Current industrial efforts promote the use of large area electronics in panel or sheet format or rolls from reel-to-reel. These circuits will consist mainly of interconnects for low density display applications or for solar panels.
It is desired to make solar systems as light and efficient as possible especially for space applications. The highest efficiencies to date of 30%, and more recently 40%, have been achieved in multijunction single-crystal solar cells fabricated in III-V semiconductor compounds. The cells are up to 10 microns thick and are epitaxially grown on germanium (Ge) or gallium arsenide (GaAs) substrates, which are rigid and require heavy support structures. Thinning of the semiconductor wafer reduces the weight but makes it brittle. To date there has not been a suitable flexible substrate that protects the fragile thin cell and serves as a permanent carrier, which is scaleable to large panels.
There are three types of solar cells: thin films, which are usually polymeric or amorphous silicon and which can be deposited on large panels a few square meters in size made of glass substrates or flexible plastic sheets using roll-to-roll manufacturing processes. These films are fabricated at low temperatures compatible with the flexible substrates and have efficiencies below 10%. Other more efficient materials, such as copper indium gallium selenide (CIGS) or cadmium telluride (CdTe), which is a polycrystalline II-VI compound, have also been used to fabricate the thin-film solar cells. The use of thin-film photovoltaic cells could lead to a reduction in the cost of solar panels but would require larger areas due to the low efficiencies of the cells. The second type of solar cells are single or poly-crystalline silicon grown on silicon wafers, and contain indium, which is a rare and expensive metal that contributes to the high cost of solar panels. These cells achieve efficiencies between 15 and 20%. The vast majority of solar panels in use today are based on silicon cells. The third type of solar cells with the highest efficiency are made of III-V semiconductor compounds and fabricated on GaAs or Ge wafers. Recent advances in III-V multijunction solar cell design have resulted in a metamorphic lattice mismatched GaInP/GaInAs/Ge 3-junction cell with 40.7% efficiency. These cells are fabricated on their native substrates at very high temperatures and have attained efficiencies over 40%, double the efficiency of conventional silicon solar cells. The total thickness of the three junctions is about 10 microns. Two such cells typically share a 4″ Ge wafer for space applications. Cells that are designed for terrestrial use have smaller areas of about 1 mm2 and are used in conjunction with concentrators that focus the solar radiation.
Unlike silicon solar cells, which utilize a single junction, the multijunction technique features three stacked photovoltaic (PV) layers each with different bandgap energy. Light across a broader spectrum is captured and converted into electricity. The cell consists of GaInP (for short wavelengths), GaInAs (middle part of spectrum), and Ge for capturing IR. The breakthrough efficiency was the result of the lattice mismatch. These multijunction solar cells were developed primarily for powering spacecraft but are starting to appear in terrestrial applications. Currently, cells with 4 junctions are being experimented. Concentrator solar cells with efficiencies of 36% are currently being mass-produced and shipped and plans for producing cells with efficiencies of 42% by 2010 are underway.
It is contemplated to use the highest efficiency cells for space applications to power satellites in order to reduce the weight at lift-off. The ultimate goal of solar cell fabrication is flexibility and scalability because large areas are required to capture sufficient solar radiation to generate substantive electrical power. It would be necessary to thin the Ge or GaAs wafer to make it lightweight and flexible. The key factor is not the substrate weight or thickness, but the implications on module design and packaging. Thick wafers are brittle and need protection from mechanical stress, hence the heavy support structures. The Holy Grail of solar panels is a module that can be bent and still functions. This precludes the use of thick glass front plate on the solar panel.
Ge wafers carrying multijunction solar cells have been glued to Kapton tape up to a few mils thick using materials such as Teflon. The single crystal cells were thinned either by grinding away the Ge base or by incorporating sacrificial layers, which were subsequently etched to lift-off the thin cells. The Kapton serves as a temporary carrier for handling the thin layers. The lightness and flexibility of the Kapton allows reaching specific powers in excess of 1000 W/kg, but the problem with Kapton is its lack of stability at high temperatures and the variation of its thermal properties with temperature. For example, the coefficient of thermal expansion (CTE) of Kapton, according to the manufacturer's spec sheet, jumps from 18 ppm/° C. between 23 and 100° C., to 31 ppm/° C. between 100 and 200° C., to 48 ppm/° C. between 200 and 300° C., up to 78 ppm/° C. between 300 and 400° C. This wide variation causes uneven expansion and stress in the thin films at high temperatures. High temperature properties of the carrier are important because the thin cell is further processed for backside metallization after lift off. Kapton does not have the quality to serve as a permanent carrier.
The technique of layer transfer by bonding and subsequent thinning of the wafer was developed in conjunction with 3-D circuit integration and SOI technology. For example, a high performance circuit is fabricated on an SOI wafer. The SOI layer may include silicon device islands as small as 5 μm×5 μm×100 nm buried under silicon oxide layers and connected by metallic lines with a total thickness of up to a few microns. The SOI wafer is temporarily bonded to an intermediary or handle wafer using dissolvable epoxy. The handle wafer is usually made of glass, which permits visual alignment of the wafers. The SOI wafer is thinned by a combination of backgrinding and etching. The buried oxide of the SOI serves as the etch stop layer. After thinning, the thin SOI layer with devices sits upside down on the handle wafer. Subsequently, the glass wafer with the inverted circuit is bonded to the host wafer using permanent adhesive, such as BCB. The host wafer is usually a silicon wafer. The epoxy between the glass wafer and the SOI layer is dissolved during the BCB curing process, thus freeing the handle wafer to be reused. Alternatively, the epoxy layer can be ablated with laser through the glass wafer. After the second transfer the SOI circuit layer faces upwards on the host wafer. The entire procedure is repeated to build 3-D circuits on the host wafer. Vias with cross-sections less than 10 μm×10 μm are dry etched in the successive layers and metallized to provide vertical interconnects among the layers. This also provides multi-gate access. The SOI devices can be ultra-thin, less than 50 nm. The entire SOI layer including all silicon devices, metal and oxide layers could be less than 1 μm thick. This is the standard procedure for stacking silicon circuit layers by lifting off the SOI layer. This procedure is similar to the fabrication of bare SOI wafers except that the layer is transferred after the circuit is fabricated. The thinning procedure is also used to provide efficient means of heat dissipation for high-speed high performance devices made of III-V compounds. This procedure sacrifices the original donor wafer. Alternatively, sacrificial layers can be incorporated in the Ge or GaAs wafer, which permit lift-off of the thin epi-layer and reuse of the donor wafer. The handle and host wafers provide continuous support for the thin layer throughout the thinning process. This is safer than thinning of silicon chips by mounting temporarily on tapes and circumvents the risks associated with handling the thin layer. The lift-off process described above is less risky because the thin layer is continuously supported. IBM demonstrated successful transfer of pre-fabricated single crystal silicon circuit layer to silicon host substrate in 2003.
High performance single crystal silicon devices and circuit layers have not been transferred to flexible substrates. Epitaxially-grown multi-junction solar cells on Ge and GaAs substrates have not been transferred to flexible substrates.
It would therefore be desirable to provide a flexible polyimide substrate and a polymer laminate wherein the materials used for the different layers are highly compatible in terms of thermal, mechanical, chemical and machining properties.
It would also be desirable to cost-effectively fabricate, for example, by laser machining in a polymer or a polymer laminate a micro-structure, for example, a cantilevered waveguide.
It would also be desirable to fabricate an opto-mechanical device, such as an accelerometer or optical switch incorporating a micromachined cantilevered waveguide.
It would also be desirable to fabricate a micro-mechanical device in a flexible polyimide substrate, which can be actuated with low electrical power.
It would also be desirable to couple light efficiently and passively between a single mode fiber and a single mode waveguide.
It would be desirable to provide a multi-layered polyimide substrate with a three-dimensional high density interconnect consisting of holes less than or equal to 50 μm diameter and pitch less than or equal to 100 μms, and to eliminate the adhesive layers between successive layers of the substrate.
It would be desirable to provide a silicon wafer bonded to a polyimide substrate.
It would be desirable to provide a thin silicon layer bonded to a polyimide substrate.
It would also be desirable to provide a thin silicon layer with a circuit bonded to a polyimide substrate.
It would be desirable to provide a Ge or GaAs wafer bonded to a polyimide substrate.
It would be desirable to provide a thin Ge or GaAs layer bonded to a polyimide substrate.
It would also be desirable to provide a thin epitaxially grown Ge or GaAs layer with a solar cell bonded to a polyimide substrate.